Low-complexity multiplier for gf (2m) based on all-one polynomials

×

Error message

User warning: The following theme is missing from the file system: journalijdr. For information about how to fix this, see the documentation page. in _drupal_trigger_error_with_delayed_logging() (line 1138 of /home2/journalijdr/public_html/includes/bootstrap.inc).

International Journal of Development Research

Low-complexity multiplier for gf (2m) based on all-one polynomials

Abstract: 

This paper presents an area-time-efficient systolic structure for multiplication over GF(2m) based on irreducible all-one polynomial(AOP). We have used a novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay. It is further shown that the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input operand, and they can share the same input operand registers. From the application-specific integrated circuit and field-programmable gate array synthesis results we find that the proposed design provides significantly less area-delay and power-delay complexities over the best of the existing designs.

Download PDF: