The paper endeavours to unveil a design strategy to retain the true nature of the output in the event of occurrence of faults at the interconnect level of cascaded digital circuits. The operational pattern of the combinational circuit facilitates the creation of a self healing attribute and ensures the reliability of the digital architecture. The proposed scheme inserts faults randomly into the system at the interconnect levels and fosters to predict its behaviour in response to a fault. The scheme be-hives the formation of a self checking mechanism to aid in the process of analysing the signals at different stages for both stuck at 0 and 1 faults. The design encompasses ways to intrigue the state of the intermediate signals and carries it with steps to rig out the true values at the primary output lines. The Modelsim based simulation results obtained for a decoder designated as the circuit under test emphasize the suitability of the scheme and avail the attributes of an FPGA to exhibit its practical viability.
Prof. Dr. Bilal BİLGİN